The following commonly-assigned prior art references are considered to be the most pertinent to the present invention:
1. U.S. Pat. No. 4,945,538, granted Jul. 31, 1990, entitled "Method and Apparatus for Processing Sample Values in a Coded Signal Processing Channel." PA0 2. U.S. Pat. No. 5,282,216, granted Jan. 25, 1994, entitled "High Data Rate Decoding Method for Coded Signal Processing Channel." PA0 3. Application U.S. Ser. No. 07/526,878, filed May 22, 1990, now U.S. Pat. No. 5,291,500 entitled "Eight-Sample Look-Ahead for Coded Signal Processing Channels."
Each of the references 1-3 discloses a (1,7) maximum likelihood (ML) coded signal processing channel comprising a (1,7) ML decoder that uses (i) a known current state of the channel, denoted by the three most recent bits (a.sub.0, b.sub.0, c.sub.0) of the (1,7) coded sequences in NRZ notation, and (ii) five or more digital sample values, denoted y.sub.0, y.sub.1. . . y.sub.n, derived from an analog read signal to determine the next state of the channel, denoted (a.sub.1, b.sub.1, c.sub.1).
There are four states, (000, 100, 111, 011) for which decisions are required. Part of the decision process is to compute the values of certain linear functions of the digital sample values and compare the result to a boundary threshold value, which depends on the current state of the channel, using a hardware comparator. For example, one such comparison is: EQU [y.sub.0 +2y.sub.1 +y.sub.2 ].ltoreq.K(a.sub.0, b.sub.0, c.sub.0)
where K(a.sub.0, b.sub.0, c.sub.0)is a predetermined state-dependent constant.
Since this comparison depends on the current state, either the current state must be known prior to beginning the comparison, or, alternatively, all four possible comparisons must be made; and then later, when (a.sub.0, b.sub.0, c.sub.0) is known, only the correct comparator output must be used. If the comparison is delayed until the state (a.sub.0, b.sub.0, c.sub.0) is known, the decoding process is slowed down, and the data rate of the channel is limited. On the other hand, if the comparisons are performed for all four possible states, four times as much hardware and four times as much power will be required than is really needed.
In References 1-3, the detected phase c.sub.0 of the current state was fed back to a set of sign change blocks to change the sign of the incoming precomputed linear functional expressions of the digital sample value for the next state whenever the c.sub.0 bit in a state register had a value of "1" corresponding to the negative state phase. By thus predetermining the correct phase (positive or negative) of the next state, one set of comparators could be used to perform the comparison step, thereby halving the number of comparators required. However, in a high-speed implementation, c.sub.0 could not be computed quickly enough to change the sign of the precomputed linear functions before the comparison step.
There is a need for an improved (1,7) ML channel embodying a hardware implementation that significantly reduces circuitry and power requirements with no sacrifice in data rate. For disk storage products used in personal computers and laptop computers, power consumption in read/write electronics must be extremely constrained.